This invention relates to a resistor string digital-to-analog (hereinafter referred to xe2x80x9cD/Axe2x80x9d) converter.
In resistor string D/A converters, resistors having the same resistance value with each other are connected in series, and voltages at respective junctions between the resistors are selectively output as an analog voltage corresponding to data for conversion. Accordingly, to convert data having an increased number of bits, the D/A converter is required to have a correspondingly increased number of resistors. This is very undesirable, particularly when a D/A converter of this type is formed within a small chip area of a semiconductor integrated circuit, since a large area of the chip is occupied by the resistors of the converter, and depending on the number of data bits, it is impossible to form the D/A converter. To solve this problem by reducing the number of resistors, it has been employed to generate a voltage corresponding to less significant bits of data for conversion by a current addition method.
FIG. 3 is a circuit diagram showing the whole arrangement of a D/A converter of this type. In the figure, symbol DI designates an input terminal through which is supplied 8-bit data for conversion. The six more significant bits (second to seventh bits) of the data supplied through the input terminal DI are applied to a decoder 1, while the two less significant bits (first and zeroth bits) are applied to a current addition circuit 2. Reference numerals r0 to r63 designate resistors connected in series and having the same resistance value (R2) with each other. Reference numeral 3 designates an operational amplifier. The operational amplifier 3 has a non-inverting input thereof supplied with a constant voltage Vref, an inverting input thereof connected to a midpoint C of the resistors r0 to r63, and an output thereof connected to one end of the resistor r63. The resistor r0 has one end thereof grounded via a resistor rx. Reference numerals F0 to F63 designate FET""s each of which serves as an analog switch and is turned on and off by an output from the decoder 1.
In the current addition circuit 2, reference numeral 5 designates a terminal to which a reference voltage V1 is applied, reference numeral 6 a resistor, and reference numerals 7 to 11 FET""s. A series circuit formed by the resistor 6 and the FET 7 and a series circuit by the FET""s 8, 9 form a current mirror circuit, and the series circuit formed by the resistor 6 and the FET 7 and a series circuit by the FET""s 10, 11 form another current mirror circuit. Therefore, currents i1, i0 flowing, respectively, through the circuit formed by the FET""s 8, 9 and the circuit formed by the FET""s 10, 11 each have a value which is proportional to that of a current ir flowing through the circuit formed by the resistor 6 and the FET 7. The FET""s 8, 10 are turned on and off, respectively, by the first bit and the zeroth bit (LSB) of the data for conversion. Reference numeral 14 designates an operational amplifier. The operational amplifier 14 has a non-inverting input thereof connected to a voltage at a common junction of the FET""s 0 to 63, an inverting input thereof connected to a common junction of the FET""s 8, 10, and an output thereof connected to an analog output terminal DO of the D/A converter. Further, a feedback resistor ra (resistance value R1) is inserted between the output of the operational amplifier 14 and the inverting input of the same.
In the D/A converter constructed as above, a voltage at the midpoint C of the resistors r0 to r63 is equal to the constant voltage Vref. Accordingly, a constant current i determined by the constant voltage Vref flows through the resistors r0 to r63. Consequently, a voltage drop across each of the resistors r0 to r63 is expressed as follows:
ixc3x97R2
On the other hand, the gate width of the FET 11 is adjusted in advance such that the current i0 which flows through the FET 11 when the FET 10 is in the ON state satisfies the relationship expressed by the following equation:
i0xc3x97R1=ixc3x97R2/4
Similarly, the gate width of the FET 9 is adjusted in advance such that the current i1 which flows through the FET 9 when the FET 8 is in the ON state satisfies the relationship expressed by the following equation:
i1xc3x97R1=ixc3x97R2/4
As a result, a current corresponding to the two less significant bits of the data for conversion flows through the resistor ra, whereby a voltage corresponding to the two less significant bits is developed across the resistor ra. On the other hand, the six more significant bits of the data for conversion are decoded by the decoder 1, and one of the FET""s F0 to F63 is turned on by the decoded output from the decoder 1, whereby a voltage at one of the junctions between the resisters r0 to r63 which corresponds to the FET that is turned on is supplied to the non-inverting input of the operational amplifier 14. The operational amplifier 14 adds the voltage supplied to its non-inverting input and the voltage drop across the resistor ra, and then outputs the result of the addition via the output terminal DO as an analog voltage corresponding to the data for conversion.
In the above conventional D/A converter, since the current i which flows through the resistors r0 to r63 and the current ir which flows through the circuit formed by the resistor 6 and the FET 7 are determined by the respective different circuits, the voltage width of 1 LSB differs between the six more significant bits and the two less significant bits due to variations in characteristics of the resistors, transistors, etc. caused by the manufacturing process. For instance, a variation in the current ir due to a variation in the threshold value Vt of the FET 7 causes a change in the voltage width of 1 LSB of the two less significant bits. Consequently, the conventional D/A converter suffers from lowered conversion accuracy, particularly when the number of data bits is large.
The present invention has been devised to eliminate the above stated inconvenience, and it is an object of the invention to provide a D/A converter that is free from a variation in the voltage width of 1 LSB between the more significant bits and the less significant bit due to variations in characteristics of resistors, transistors, etc. to thereby ensure higher conversion accuracy than the conventional D/A converter.
To attain the above object, the invention provides a digital-to-analog converter comprising a plurality of resistors connected in series, selection means that selects one of voltages at respective junctions between the plurality of resistors, based on M (M: an integer which is larger than 1) more significant bits of data for conversion, current output means that generates a current having a value which is proportional to a value of a current flowing through the plurality of resistors and corresponds to N (N: an integer which is larger than 1) less significant bits of the data for conversion, a conversion resistor that converts an output current from the current output means to a voltage, and an operational circuit that performs an operation on the voltage selected by the selection means and a voltage developed across the conversion resistor, wherein the current output means comprises a control transistor serially connected to the plurality of resistors connected in series, for controlling the current flowing through the plurality of resistors, and first to N-th transistors each controlled by a voltage identical to a voltage at a control terminal of the control transistor and each cooperating with the control transistor to form a current mirror circuit for outputting a current having a value which is proportional to a weight assigned to a corresponding one of the N less significant bits of the data for conversion, each of the first to N-th transistors being turned on and off by a corresponding one of the N less significant bits.
Further according to the invention, the digital-to-analog converter is characterized in that the selection means comprises a decoder that decodes the M more significant bits of the data for conversion, and a plurality of switch means each of which selects a corresponding one of voltage values at the respective junctions between the plurality of resistors, based on an output from the decoder.
Further according to the invention, the digital-to-analog converter, is characterized in that the operational circuit has a first input to which an output from the selection means is applied, a second input to which an output from the current output means is applied, and a feedback loop into which the conversion resistor is inserted.